1.1—Technical Field
The inventions herein relate to Cooling Systems, especially to cooling of electronics systems, and especially to cooling of high power electronic packages and components, which generate a lot of heat, which needs to be spread, removed and dissipated.
More particularly, the inventions relate to situations, where the heat flux (heat per unit area) coming out of the heat source is excessive, i.e. higher than what the heat dissipation/cooling system can handle. In such situations, it is recommended to use a so-called “heat spreader” to distribute or spread the heat over a larger surface area, thus reducing the heat flux down to manageable (lower) levels. So, the present inventions relate to such heat spreaders and related devices. This can be interpreted as the “Heating Spreading Problems.”
In another particular area, the inventions herein relate to cooling situations, where the components are made of different materials, which have different Coefficients of Thermal Expansion (CTEs), in which case, it is said that the components, especially the heat source and the heat sink, have a CTE mismatch. This CTE mismatch is considered as one of the major Interface Problems in Cooling Systems.
All the above is addressed by the present inventions.
1.2—General Problem
1.2.1—Excessive Heat Flux and Related Heat Spreaders.
In certain cases, the heat flux (heat per unit area) coming out of the heat source, such as an electronic package, is excessive, i.e. higher than what the heat dissipation/cooling system can handle, and can affect the capability of the Cooling System in certain particular situations. A good example, is when the heat flux is in the range of 300 W/cm2. In such situations, it is desirable, if possible, to distribute or spread the heat over a larger surface area, thus reducing the heat flux to manageable levels. This is done sometimes by using “Heat Spreaders”.
1.2.2—CTE Mismatch
One of the most frequently used methods for cooling electronic components is to attach a heat sink on top of the component, which we would call the heat source. Also most frequently, the components are made of different materials, having different Coefficients of Thermal Expansion (CTEs). For example, the source of the high amount of heat could be a Chip Carrier (CC), which is most frequently made of Ceramic, which has a CTE of ˜6 PPM/K. Then a heat sink is attached to the top of the CC to conduct the heat out from the CC and to dissipate that heat into the surrounding environment or to conduit that heat to some central cooling system. The heat sink could be made of Aluminum (CTE of 23 ppm/K) or of Copper (CTE say 17 ppm/K). After the heat sink is attached to a heat source, we can say that the components, i.e. the heat source and the heat sink, have a CTE mismatch.
If there is a CTE mismatch, as described above, then problems can arise and the cooling effect can be compromised and could fail.
1.2.3—Interfaces, including TIMs
Frequently in situations as those mentioned above, where a heat sink is used to dissipate heat generated from an electronic device, a Thermal Interface Material (TIM) is applied between the source and the sink. TIM can act as a filler, to compensate for irregularities in the surfaces of the source and/or the sink, and can act as a “GLUE”, as well.
Sometimes the heat sink is soldered or brazed or otherwise permanently attached to the heat source.
1.2.4—Composite Materials
One of the recent popular trends and approaches to solve the above problems is to use certain “COMPOSITE MATERAILS”, which have CTE values that match, as close as possible, the CTE of the heat source and/or the heat sinks. See for example, Section 1.5.5 OTHER RELATED THIRD PARTY REFERENCES: REF. 1—Zweben, C.; “Ultrahigh-thermal-conductivity packaging materials,”, further down in this specification. Moreover, if the electronic components and systems in question are to be used in space vehicles, then the weight of the materials becomes another issue to contend with.
1.3—Specific Problem Cases
It seems that the Air Force and NASA have anticipated that they could encounter such situations in the future and they issued two SBIR solicitations, to prepare for any possibilities.
In 2011, the Air Force has issued a solicitation to try to get any interested, capable party to submit proposals to solve certain problems related to the above ones. It was the Air Force SBIR Solicitation Topic Number: AF112-057, Title: Next-Generation Micro-Chip Carrier for Cooling of Satellite Payload Electronics.
A short time later, NASA issued a fairly similar SBIR solicitation, with fairly similar requirements.
After studying the solicitations requirements, I submitted a proposal to the Air Force and then later on, another proposal to NASA, offering almost similar solutions in both cases. I have not received any contract awards to implement the solutions, from neither parties.
Regardless of the contracts, the solicitations acted as a challenge and as an impetus for me and motivated me to come up with some solutions to the problem. The results were that I did come up with most of the inventions described in the present application and specification. And later on, I continued to work on the subject and came up with a thermal analysis, as will be described in the present specification.
I will summarize and paraphrase here below some highlights of, and excerpts from, the Air Force solicitation and requirements, and of my submitted proposal. I will concentrate on the points, which are relevant to the inventions in this application and specification.
1.4—Highlights from the Air Force SBIR Solicitation
1.4.1 The solicitation described the problem basically as follows. [I will paraphrase and re-order some sections and use only relevant excerpts and will leave out certain things that are not technical in nature.                “In order to provide the U.S. warfighter with the most capable satellite communications, payload processing power is expected to grow in density for the foreseeable future, with higher gate counts producing increased levels of waste heat. The anticipated increase in heat flux generated by next-generation electronics components is driving the need for greater heat spreading capability in the carriers to which these high-heat flux chips are mounted.        The specific objectives of the research topic are to take care of the problem below, by satisfying the following requirements:        PROBLEM: Current conduction-based heat spreading devices do not provide adequately high conductance in the x, y, and z directions and an adequate CTE-match to meet the requirements of future electronics components.        REQUIRED: Therefore, the following is required:        1. The proposed carrier should be a two-phase device that allows efficient heat transfer at the evaporator and condenser surfaces. Two-phase micro-loop heat pipe and heat pipe devices should be considered.        2. The design of the spreader should be scalable and would ideally be versatile enough to be applied to a variety of packaging configurations; however, proposers may select a single relevant packaging style if necessary.        3. Proposed solutions must have high-reliability and maintenance-free operation for lifetimes exceeding ten years.        4. The device must also be compatible with the space environment and conform to space-qualification requirements, including high vacuum, microgravity, radiation, atomic oxygen, low outgassing and high launch loads.        
1.4.2 The goal of the SBIR research is/was basically the following:                Develop innovative chip carrier cooling solution that efficiently reduces heat flux levels generated by high-power satellite components to levels manageable by the spacecraft's thermal control system.        The ultimate goal of this project is to develop an innovative spreader that maximizes the capacity of the carrier to reduce the heat flux for efficient transport of waste heat to the spacecraft primary thermal management system. This spreader must maintain a sufficient coefficient of thermal expansion (CTE) match with foreseen high-heat flux devices that may be mounted to it.        
1.4.3 Technical Objectives:                Technical Objective 1: Spread heat fluxes from >300 W/cm^2 (objective) or >100 W/cm^2 (threshold) at the chip to (<10 W/cm^2) levels manageable by primary thermal control system        Technical Objective 2: Minimize the temperature drop between the chip and primary thermal control system.=Minimize chip temperature.        Technical Objective 3: Survive temperatures from −60 C to 60 C; operate in temperatures from −20 C to 50 C.        Technical Objective 4: Require zero input power for operation and control.        Technical Objective 5: Have tailorable CTE from 4-17/C (objective) or a CTE that sufficiently matches foreseen high heat flux devices (˜6-8 ppm/C).        
1.4.4 My interpretation of the Key Phase I Technical Objective was (REPHRASED):                1. Develop innovative chip carrier cooling solution, that efficiently        2. reduces heat flux levels generated by high-power satellite components        3. to levels        4. manageable by the spacecraft's thermal control system.        
Also I visualized that the problem looks more of less as illustrated roughly in FIG. 1
The way I saw it, once we achieve these above goals and objectives, then all the rest of the objectives will be satisfied, almost automatically. I believe that the reader will agree, after you read the rest of my present specification.
1.5 Prior Art
1.5.1 Many solutions to this problem have been invented and patented.
I made an extensive patent search and did not find any solution that is similar to my present inventions or embodiments.
The closest Prior Art that I found is in U.S. Pat. No. 6,935,409 to Parish I V et al. However, Parish prior art does not teach over my present inventions here.
1.5.2 On the other hand, I have prior art myself in certain areas, that can help in solving the present problem. I will utilize some of this prior art, as a spring board, to solve the present problems, and then I will add a few new novel concepts, as well.
1.5.3 Related Prior Art Patents, by Gabe Cherian et al:                1. U.S. Pat. No. 4,664,309, “CHIP MOUNTING DEVICE”, May 12, 1987, Gabe Cherian, Co-Inventor, Raychem Corporation, Menlo Park, Calif.        2. U.S. Pat. No. 4,705,205, “CHIP CARRIER MOUNTING DEVICE”, Nov. 10, 1987, Gabe Cherian, Co-Inventor, Raychem Corporation, Menlo Park, Calif.        3. U.S. Pat. No. 4,712,721, “SOLDER DELIVERY SYSTEMS”, Dec. 15, 1987, Gabe Cherian, Co-Inventor, Raychem Corporation, Menlo Park, Calif.        4. U.S. Pat. No. 6,884,707, Apr. 26, 2005, Title: INTERCONNECTIONS [Non-Wicking Connecting Column(s)], Gabe Cherian, Inventor.        5. U.S. Pat. No. 7,196,402, Mar. 27, 2007, Title: Interconnections [Packages with Oriented Leads], Gabe Cherian, Inventor.        6. U.S. Pat. No. 7,433,201, Oct. 7, 2008, Title: Oriented connections for leadless and leaded packages [Oriented Solder Columns, or Oriented Starved Columns], Gabe Cherian, Inventor.        7. U.S. Pat. No. 7,901,995, Mar. 8, 2011, Title: Interconnections Resistant To Wicking., Gabe Cherian, Inventor.        8. U.S. Pat. No. 7,944,028, May 17, 2011, Title: TFCC™ and SWCC™ Thermal Flex Contact Carriers, Gabe Cherian, Co-Inventor.        
1.5.4 Related Reference Papers, by Gabe Cherian et al:                1. Cherian, Gabe, “Use of Discrete Solder Columns to Mount LCCC's on Glass/Epoxy Printed Circuit Boards”, Raychem Corporation, Menlo Park, Calif.; 4th Annual International Electronics Packaging Conference, Baltimore, Md., Oct. 29-31, 1984.        2. Cherian, Gabe, “Solder Columns for Surface Mounting of Leadless Ceramic Chip Carriers on Glass/Epoxy Printed Circuit Boards”, Raychem Corporation, Menlo Park, Calif.; ISHM '85, 1985 International Symposium on Microelectronics, Anaheim, Calif., Nov. 11-14, 1985.        3. Cherian, Gabe; Wynn, Craig; White, Harry, “New Solder Column Alloy improves Reliability of Chip Carrier Assemblies”, Raychem Corporation, Menlo Park, Calif.; 1986 SAMPE, Seattle, Wash., 18th International SAMPE Technical Conference, Oct. 7-9, 1986.        4. Cherian, Gabe, Cherian Enterprises, Sun Valley, Id.; “BGA MOUNTING USING IMPROVED SOLDER COLUMNS”, IPC Printed Circuits EXPO 2003, Long Beach Center, Long Beach, Calif., Mar. 23-27, 2003.        5. Gabe Cherian, Cherian Enterprises, Sun Valley, Id., “Higher Reliability Oriented Plastic Packages”, IPC ECWC10 Conference, IPC Printed Circuits Expo®, SMEMA Council APEX® and Designers Summit 05, Anaheim, Calif., February 2005.        6. Cherian, Gabe, Cherian LLC, Sun Valley, Id.; “Fighting the Undesirable Effects of Thermal Cycling”, IPC APEX EXPO 2010, Las Vegas, Nev., Apr. 8, 2010.        
1.5.5 Other Related Third Party References:    REF. 1—Zweben, C.; “Ultrahigh-thermal-conductivity packaging materials,” Semiconductor Thermal Measurement and Management Symposium, 2005 IEEE Twenty First Annual IEEE, vol., no., pp. 168-174, 15-17 Mar. 2005.    REF 2 Heat Pipes, Theory, Design and Applications, by David Reay and Peter Kew, BH Butterworth-Heinemann/Elsevier, Fifth Edition, 2006.    REF 3 Spacecraft Thermal Control Handbook, Volume 1: Fundamental Technologies, by David G. Gilmore, Editor, The Aerospace Press, 2002.    REF 4 Space Mission Analysis And Design, by James R. Wertz and Wiley J. Larson (editors), Space Technology Library, Space Technology Series, Third Edition, Microcosm Press and Springer, 1999.
1.6 Analysis of the Problem and its Sources—Interfaces and Materials
1.6.1 I am including in this specification a number of drawings, which illustrate some of the basic concepts that I would like to propose as solution to the present problem in general, and to the specific problem described in this Air Force Research Topic solicitation. First I will describe the present existing way of assembling the components, and which is really the source of the problem, the way I see it. And then I will describe my proposed solution(s).
First I will describe the present existing way of assembling the components, the way I see it, and which seems to be the major possible source of the problem. And then I will describe my proposed solution(s) in later sections of this specification.
1.6.2 Please refer to FIG. 1. The major existing problem boils down to the fact that it is created by the “interfaces” (2) between the source of heat (1), which is the chip in its chip carrier, and between the heat drain or the heat sink (3), which includes the heat pipes, loop heat pipe, etc (LHP) (3), which then transfers the heat to the satellite prime thermal control system (TCS) (4). It is like a chain link effect.
Usually, the so-called conventional approach includes a component, usually called Thermal Interface Material (2), made of some good thermal conductive material, which gets attached to the top surface of the chip carrier [CC] (1), to take the heat away from it and pass it on to the next transfer device (3), which in this case will most probably be, and seemingly is the preferred method, which is to use some sort of heat pipe, loop heat pipe, or such two-phase heat transfer device. I will refer to the all of those as the Loop Heat Pipe(s) [LHP] (3).
1.6.3 So the chain so far looks like this. We have the CC (link #1), sending the heat to the TIM (link #2), which send it to the LHP (link #3). We could extend the chain to the satellite prime thermal control system (TCS) (4), if we want to, but I will limit the discussion here to these first links only.
1.6.4 Now, we can see that we could have a problem at the interfaces between link #1 and link #2 and between link #2 and link #3, and of course similarly down the line to the TCS, if there are any more interfaces in the TCS system.
1.6.5 Each one of these interfaces can have a number of negative effects.
1. The surfaces of these links in the chain, especially the heat source (1) and the heat sink (3), are not perfectly flat. They usually have some irregularities, hill and valleys, etc. If we try to hold one link against the next, we will have some air gaps, which will hinder the smooth flow of heat from one link to the other. So, the common procedure is to insert a Thermal Interface Material (TIM) (2) in between, where this TIM usually is a relatively soft material, which can conform and fill these gaps to create a more intimate surface to surface contact, so as to improve the transfer of heat. In addition, the TIM is usually chosen to be a good heat conductor, or may contain other materials in it, which in themselves are good heat conductors, and which can transfer the heat more easily. All this is done, so as to hopefully have less thermal resistance to the flow of heat.
2. Now, we have a first interface between the starting (upstream) link (1) and the TIM (2), and then a second interface between the TIM (2) and the second (downstream) link (3).
3. But this way, now we have essentially doubled the number of interfaces. See the effect of that later down below.
4. Now back to the interfaces. At every interface, we “face” [no pun intended] an important problem. Most probably, the materials of the links in the chain are different, and each one of these materials has its own Coefficient of Thermal Expansion CTE. And more often than not, these CTEs have different values. And this is the next critical issue. We know what it is.
5. When the links in the chain get heated or cooled, they will expand or shrink at different rates. So, we will have some differences in their length, along the interface surfaces between them. Let's visualize now the result of such linear differential.
6. Delamination at the interfaces due to excessive shear stresses
I will digress here and try to explain some of the key factors that affect cases, where two components are attached together and the potential problem, mainly the delamination, that can result from that.
When two components are attached to each other, to create a laminate, e.g. an Electronic Integrated Circuit Package (ICP) and a Printed Circuit Board (PCB), or a heat source and its heat sink, where these two attached components are made out of two different materials, and where each one of these two materials have its own respective and different Coefficient of Thermal Expansion (CTE), i.e. where we say that the two components have a CTE mismatch, then we may have problems, when the laminate temperature changes. When we change the temperature of the components, they will expand or contract at different rates. More generically, we can say that they will have different linear deformations, where their length will change, based on the magnitude of the temperature change, and on their individual initial length, on their individual CTE.
FIG. 2 illustrates such a condition. The lower figure shows a laminate, made out of two slab components, attached together with some sort of glue, applied at their interface. We will assume that the lower slab has a small CTE, while the upper slab has a larger CTE.
The lower figure shows the laminate at a rest condition, say at room temperature, where the two slabs have exactly the same length.
The upper figure shows what would happen if the laminate is heated to some high temperature. Both slabs will expand, but at different rates. The linear deformation of the upper slab will be larger than the linear deformation of lower slab, due to its larger CTE, as can be seen at the outer extremities of the slabs.
However, we have to keep in mind that the linear deformation is proportional to the original length of the components. So, towards the center of the slabs, the linear deformation is relatively small compared to the corresponding linear deformation near the end of the slabs. As a result, the “difference” between the linear deformations of the two slabs, will be small near the center of the slabs, compared to the “difference” near the ends of the slabs.
This “difference” in the linear deformation is very crucial.
When the slabs deform at different rates, then their surfaces along their interface will have to slide with respect to each other. This is true, only if the two slabs are free to slide and if the laminate is not allowed to warp or curl.
But if the two slabs are physically attached together, with a glue or the like, as it is shown in our case here, then this sliding action has to be absorbed by the glue holding the two slabs together. If the amount of sliding can be absorbed by the glue, then everything will be fine. The glue will be stressed, but if the stress is within the stress limit of the glue, then it is OK.
But if the magnitude of this sliding is more than what the glue can withstand, then the glue can rupture, break down, and fail.
In more scientific terms, we can say that the glue gets over-stressed.
And because of the geometry and configuration of the glue at this interface, then this kind of stress is called shear stress, mainly because the thickness of the glue is relatively small.
If we analyze the magnitude of the shear stress in the glue, we can find that the value of the shear stress can be represented by the triangular shape shown in FIG. 3.
The shear stress starts with a zero value at the exact center of the slabs. The shear stress will increase, linearly, as we go away from the center, in any direction, as represented by the graph, which in this case, looks like two triangles, with their smallest value being at the center of the slabs and which increases as we go out towards the edges of the slabs. So, at one point we will reach a stress level that corresponds to the max stress that the glue can withstand. Beyond that point, we should expect that the glue would break down, crack open and we would get some kind of failure, which ultimately will end up with a separation between the two slabs. The graph in FIG. 3 shows the good, safe range or zone as the areas marked “Y” for “YES” or safe, and the bad, dangerous area or zone as the areas marked “N” for “NO” or dangerous or overstressed.
The most probable end result is illustrated in FIG. 4. The areas that were in the “N” zones in FIG. 3 will fail and eventually would delaminate. Those areas of the joint between the slabs may separate, may even curl up away from each other, and we could see that the slabs may pull away from each other, and may ultimately delaminate.
If we are relying on a set up like this to transfer heat from one of the components to the other, then with such a delamination, we will not get as much heat transfer as we would expect before such delamination.
7. Now, let's apply the above analysis to our present problem. Let's say, that the CC is made of Ceramic, CTE around 6 ppm/K, and that the HS right above it is made of Copper, CTE say 17 ppm/K. See FIG. 6 for a similar situation between a BGA and a PCB. This means that if their temperatures rise by one degree, the Copper HS will expand 17 ppm of its original length, while the ceramic CC will expand only 6 ppm of its same original length. This means that the copper will expand approx 3 times as much as the Ceramic CC. This means that the linear difference between the parts will be=17−6=11 ppm/K of the actual original length.
8. If the dimension of these two links is small, this 3-fold linear differential could be so minute, that it would hardly have any consequence. See the middle portion of the laminate in FIG. 3. But if we have a CC that is, say, over 1 cm on the side and if the temperature rises by, say, 50 C or 100 C, then we can start to see that the resulting linear differential can become more crucial. Why? Because one link will start to “slide” along their interface surfaces, with respect to the adjacent link, especially near the extremities of their length.                All this is true, assuming that the laminate is rigid enough, so that it would not “bend” or “warp”, or that it is forcefully maintained in a straight line.        But, if the laminate is fairly thin and/or if it is allowed to flex, bend and/or warp, then it would curl upward or downward, according to the changes in temperature. It would act in a similar fashion as the sensing element in, say a room temperature controller.        So for our own present application, we will continue our analysis, assuming that the laminate will not flex or curl, but it will maintain its “straight” shape.        
9. Near the center of the interface area, say within 2, 3, or even 4 mm, the sliding amount may still be small enough to be inconsequential, but once we go beyond that, it can start to create some problems. Of course, this would depend on the magnitude of the temp change, etc.
10. If the two links are, say, soldered together, and usually the thickness of the solder layer is fairly small, thin, then the solder “joint” can get overstressed. And bear in mind that the stresses in this case, i.e. the thin solder joint layer, are predominantly “shear” stresses. And the thinner the joint, the higher the shear stresses. See the left hand side figure of FIG. 7.
11. If the shear stress exceeds the ultimate limit, then we would get cracks in the solder joints and possibly would get open gaps. Hence, the heat flow and the heat transfer will decrease. Analogous to the conditions shown in FIGS. 3 and 4.
12. Also, if the stress is not that high, but if this condition gets repeated often and we get frequent thermal cycling, then the effect of such cumulative high shear stresses can reach a point, where the joint would exceed its fatigue limit, and the joint would fail. This means that the solder joint would now crack and create some gap(s) between the two links. And we get delamination between the two links, at least near the outside areas of the joint, where the shear stresses have exceeded the limits. And we're back to where we started, with gaps between the two links, which will affect/reduce the heat flow, etc, and the bad results will get worse.
13. So, another conventional way to overcome this potential problem situation is to insert the above mentioned TIM between the two links. And more often than not, the TIM works very well, and it reduces the air gaps, plus it can also act as a “glue” as well, besides being just a gap filler. But again, with large size CCs and with large thermal swings, we can get almost the same kind of cracks and delamination as explained earlier, but now they will be between the individual links and the TIM itself.
14. So, another way to overcome the general problem is to try to use materials for the two links, which have similar CTEs, or where the adjoining materials have CTE values that are as close to each other as possible. And this is the main effort and thrust of a lot of present research work, trying to find such materials, which first need to be good thermal conductors and at the same time, which would have CTEs that match closely the CTEs of the heat source, which is most frequently made of ceramic, and obviously, the CTEs—of the heat sink as well, which may have a different CTE. And in addition, if these materials are intended to be used in space applications, then their weight would be another big factor to consider.
15. So, experts, like Dr. Carl Zweben, the author of one of the referenced papers, see Ref #1 listed in section 1.5.5 “OTHER RELATED THIRD PARTY REFERENCES”, above in the present specification and one of my intended consultants for the SBIR proposal, apply their efforts to find such materials. Fortunately, they did find quite a few of such materials, as listed in Dr. Zweben's papers and in so many other papers and articles on the subject. I can still use these materials in my proposed solutions, and they can enhance the advantages of my solutions, as will be seen down below.
16. Now, we ought to consider one more small potential source of problem, even with these special materials. Say, we make the HS out of Invar, which has a CTE of 6.5, practically identical to the ceramic's CTE of 6. We will still have an interface between it and the CC. This interface will have a certain thermal resistance, which will result in a temperature differential, say “Delta T” or DT. The effect of this DT is that the two links will be at a different temperature, hence they will expand or contract by a different amount. Here, somebody could say that I am splitting hairs. I know that I am. This is quite true, if the heat flux is relatively mild. But when we start to talk about a heat flux of 300 W/cm2 and over, then the difference in temperatures can start to be appreciable. And we could end up with similar delamination etc.
17. This above analysis will help us in finding the possible solutions. Please see down below.
1.7 Prior Art Work Related to CTE and Interface Problems.
1.7.1 Again, before I get into my proposed solution, let me described what I have done, over 25 years ago, to solve another problem, which is very much similar to the present one. Actually, it is identical to the present problem, except that it is “on the other side” of the Chip Carrier. It is BELOW the chip carrier instead of being above it.
1.7.2 Let's look at the general way we assemble such chip carriers (CCs) onto Printed Circuit Boards (PCBs). Please see FIGS. 5 and 6. Please refer also to the References, covering the CCMD papers and patents. Most probably, the CCs are like the BGAs, FIG. 5, which are the popular packages nowadays. Or they can be like the old Leadless Ceramic Chip Carriers (LCCCs), which were popular some 25-30 years ago. In both cases, when such a CC gets attached to a PCB, they get attached together with solder joints. These joints can start as solder paste, solder cream, applied to the pads of the PCB, or as solder balls, applied to the CC, as in FIG. 5, hence its name BGA, Ball Grid Array Package. Now, when the CC gets attached to the PCB, the resulting solder joints are usually short and stubby, as in the middle figure of FIG. 6. This is point #1 to keep in mind. Short and stubby.
We also realize that the BGAs are usually made of ceramic, CTE around 6 ppm/K, while the PCBs are usually FR4 or the like, CTE around 18-24 ppm/K. This means that the PCB will expand or contract some 3-times to 4-times as much as the BGA, when their temperature would rise or fall. This is illustrated in FIG. 6. This is point #2 to keep in mind. Three to four time CTE mismatch.
1.7.3 So, what is the result of these two important points?
1.7.4 When such an assembly gets hot, as in the top figure FIG. 6, the PCB expands more than the BGA and the solder joints at the extreme ends of the row of joints will be deformed as shown. We will call this condition, the hot stress deformation, where the solder joints are deformed or pulled outwards.
When the assembly gets cold, the reverse happens, as in the bottom figure of FIG. 6, the PCB contracts/shrinks more than the BGA and the solder joints at the extreme ends of the row of joints will be deformed as shown. We will call this condition, the cold stress deformation, where the solder joints are deformed or pulled inwards, i.e. in the opposite direction of the hot stress deformation.
As the temperature cycles from hot to cold, the solder joints keep on getting stressed outwards and inwards, or pushed and pulled, at every temperature cycle. After a certain number of such temperature/thermal cycles, the cumulative stresses in the solder joints could reach, and eventually exceed, the ultimate fatigue stress of the material, and as a result, the joints fail
1.7.5 This is very similar to the present problem that we are facing with the Heat Sinks, which are ABOVE the Chip Carrier. The solder joints, BELOW the Chip Carriers, would get overstressed and ultimately could fail due to fatigue under shear. The interface between the Chip Carriers and the Heat Sink, ABOVE the Chip Carrier, would also get overstressed and ultimately could fail due to a similar fatigue under shear.
1.7.6 Very similar to the problem that we are facing with the Heat Sinks, ABOVE the Chip Carrier. The solder joints, BELOW the Chip Carriers, would get overstressed and ultimately could fail due to fatigue under shear, when they get thermally cycled.
1.8 Summary and Recap of Analysis Observation
So, now we can summarize what we have observed and learned so far:
The problem that we are facing is affected primarily by the three following facts, which we knew since the beginning anyway:
1. Interfaces; keep them to a minimum.
2. CTE mismatches; keep in mind their undesirable effect.
3. Material characteristics, including CTE, as stated above, plus their thermal conductivity and their mechanical physical characteristics.
1.9 Related Prior Art Success Story/Accomplishment:
1.9.1 Around 1980-82-84, while working at Raychem Corporation, Menlo Park, Calif., I invented and developed a solution to this LCCC on PCB problem, which existed already since that time and earlier before.
1.9.2 Please see items 1, 2, and 3 in Section 1.5.3 and items 1, 2, and 3 in section 1.5.4. Please refer to the papers #1-4 and #6 listed under “RELATED PRIOR ART” section, further down below in this present specification, as well as the patents #7, 8 and 9.
1.9.3 We called my solution, CCMD, for “Chip Carrier Mounting Device”.
1.9.4 Please see FIG. 5.
1.9.5 Later, it was called “Solder Columns”.
1.9.6 The “column” concept was known earlier. IBM solder columns had paved the way, but with my CCMDs, I have introduced an additional “twist” onto the columns and CCMD became successful and popular. Again, see the figures in the References.
1.9.7 CCMDs were very successful and have sold in the multi-million Dollars range. An early order for the product was for $4.8 Million Dollars, from ITT for the Army SINCGARS radio, around 1983-84.
Later on, the same columns were used to attach BGAs on top of PCBs.
In 1996, Winslow Automation, San Jose, Calif. acquired the Solder Columns business from Raychem. Winslow has further developed the Solder Columns and is marketing them to this date.
1.10 Main Reasons for the Success
The reason for the success of the CCMD/Solder Columns is the use of columns themselves, which were used as the joints between the two devices.
Please look at right hand side (RHS) figure in FIG. 7.
When we place a column between the BGA and the PCB, and the temperature changes, the PCB stretches and shrinks at a higher rate than the BGA. The column absorbs the dimensional differences. The column gets strained in a way that induces bending stresses in the column.
Now here we have more control on these bending stresses, than in the case of when we have shear stresses.
Now, let's look at the RHS figure in FIG. 7, which shows the formula for the bending stresses in the column. We can see that we can reduce the bending stress, Sb, by at least two ways. One, we can reduce the diameter, “d”, of the column. Two, we can increase the height of the column, “H”. Actually, we can do BOTH, if we want to. Also bear in mind that the effect of changing the height is to the square power. None of these options is available, if the joint is under shear stress as on the LHS of FIG. 7.
A pretty extensive and lengthy, and good, MATHEMATICAL ANALYSIS was given in U.S. Pat. No. 4,664,309, see Reference #1, under Section 1.5.3, “RELATED PRIOR ART PATENTS . . . ” of this specification. Please refer to its drawings, FIGS. 1, 2, 3A and 3B. Refer also to the written analysis in the body of the patent specification, starting at Column 6, line 47 and ending at Column 9, line 28.
1.11 Related Work Success Story Still Continues
Recently, Goddard Technical Standard # GSFC-STD-6001, Approved: Feb. 22, 2011, Title: Ceramic Column Grid Array Design and Manufacturing Rules for Flight Hardware, was published and it talks about these Solder Columns, and states: “This standard establishes requirements which apply to all uses on flight hardware of ceramic-packaged electronic parts which are solder-attached to printed circuit boards with solder columns (ceramic column grid array attachments or CCGAs).”
These solder columns are the “descendents” of my original CCMDs.
More recently, I developed certain additional improvements to the original Solder Columns, which I call now “NO-WICK”™ Solder Columns, as can be seen in Cherian Related Papers, #4; in Section 1.5.4, and Cherian Related Patent #6,884,707, reference #4, in Section 1.5.2; also under PRIOR ART, listed above.
1.12 Reasoning and Logic for the Proposed Solution
So, what comes to mind now is this. Why don't we use a similar approach ABOVE the chip carrier as well? Why limit this kind of helpful solution to be used only BELOW the chip carrier? Why don't we use it also ABOVE the chip carrier, or even both under and above the CC?
Actually, above the chip carrier, the problem is less “problematic”, and can be solved with a slightly easier solution. I will describe it further down below.